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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75004, 75006, 75008
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD75008 is one of the 75X Series 4-bit single-chip microcomputer. In addition to high-speed operation with 0.95 s minimum instruction execution time for the CPU, the
PD75008 employs a serial bus interface with standard NEC format, the PD75004 is a powerful product with
a high cost/performance ratio. The PD75P008 with PROM, which is provided with PD75008, is applicable for evaluating systems under development, or for small-scale production of developed systems.
Detailed functions are described in the following user's manual. Be sure to read it for designing.
PD7500X Series User's Manual: IEM-5033
FEATURES
* Capable of high-speed operation and variable instruction execution time to power save * 0.95 s, 1.91 s, 15.3 s (Main system clock: operating at 4.19 MHz) * 122 s (Subsystem clock: operating at 32.768 kHz) * 75X architecture comparable to that for an 8-bit microcomputer is employed * Built-in NEC standard serial bus interface (SBI) * Clock operation at reduced power dissipation (5 A TYP. : operating at 3 V) * Enhanced timer function (3 channels) * Interrupt functions especially enhanced for applications, such as remote control receiver
APPLICATIONS
VCRs, CD players, telephones, cameras, blood pressure gauges, etc.
Unless otherwise specified, PD75008 is treated as the representative model throughout this manual.
The information in this document is subject to change without notice.
Document No. IC-2633C (O. D. No. IC-7673E) Date Published November 1993 P Printed in Japan
The mark 5 shows major revised points.
(c) NEC Corporation 1990
PD75004, 75006, 75008
ORDERING INFORMATION
Part Number Package 42-pin plastic shrink DIP (600 mil) 44-pin plastic QFP (s 10 mm) s 42-pin plastic shrink DIP (600 mil) 44-pin plastic QFP (s 10 mm) s 42-pin plastic shrink DIP (600 mil) 44-pin plastic QFP (s 10 mm) s Quality Grade Standard Standard Standard Standard Standard Standard
PD75004CU-xxx PD75004GB-xxx-3B4 PD75006CU-xxx PD75006GB-xxx-3B4 PD75008CU-xxx PD75008GB-xxx-3B4
Remarks: xxx is ROM code number.
Please refer to "Quality Grade on NEC Semiconductor Devices" (Document Number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
PD75004, 75006, 75008
FUNCTIONAL OUTLINE
Item Instruction Execution Time Internal Memory ROM RAM General-Purpose Registers
Function 0.95, 1.91, and 15.3 s, (Main system clock: operating at 4.19 MHz) 122 s (Subsystem clock: operating at 32.768 kHz) 4096 x 8-bit (PD75004) 6016 x 8-bit (PD75006) 8064 x 8-bit (PD75008) 512 x 4-bit * 4-bit manipulation: 8 * 8-bit manipulation: 4 8 18 CMOS Input pins CMOS input/output pins Can directly drive LED: 4 8 N-ch open-drain input/output Can directly drive LED: 8 Withstand voltage: 10V Internal pull-up resistor specification by mask option is possible. Internal pull-up resistor specification by software is possible. : 25
I/O Port
34
Timer/event counter Timer Serial Interface Bit Sequential Buffer Vector Interrupt Test Input System Clock Oscillator Standby Function Operating Temperature Range Operating Supply Voltage Package 3 chs Basic interval timer: Also serves as watchdog timer Watch timer: Buzzer output possible 3-line serial I/O mode 2-line serial I/O mode SBI mode 16 bits
3 4 6
Clock Output Function , fx/2 , fx/2 , fx/2
External: 3, Internal: 3 External: 1, Internal: 1 Main system clock oscillation ceramic/crystal oscillator Subsystem clock oscillation crysal ocillator STOP/HALT mode -40 to +85C 2.7 to 6.0 V 42-pin plastic shrink DIP (600 mil) 44-pin plastic QFP (s 10 mm) s
3
PD75004, 75006, 75008
CONTENTS
1.
PIN CONFIGURATION (TOP VIEW) ...............................................................................................
6
2.
BLOCK DIAGRAM ...........................................................................................................................
8
3.
PIN FUNCTIONS ..............................................................................................................................
3.1 3.2 3.3 3.4 3.5 3.6 PORT PINS ............................................................................................................................................. NON PORT PINS ................................................................................................................................... PIN INPUT/OUTPUT CIRCUITS ........................................................................................................... SELECTION OF MASK OPTION .......................................................................................................... RECOMMENDED PROCESSING OF UNUSED PINS .......................................................................... NOTES ON USING THE P00/INT4, AND RESET PINS ......................................................................
9
9 11 12 14 14 15
4.
MEMORY CONFIGURATION ..........................................................................................................
16
5.
PERIPHERAL HARDWARE FUNCTIONS ........................................................................................
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 PORTS .................................................................................................................................................... CLOCK GENERATOR CIRCUIT ............................................................................................................ CLOCK OUTPUT CIRCUIT .................................................................................................................... BASIC INTERVAL TIMER ..................................................................................................................... WATCH TIMER ...................................................................................................................................... TIMER/EVENT COUNTER ..................................................................................................................... SERIAL INTERFACE .............................................................................................................................. BIT SEQUENTIAL BUFFER ...................................................................................................................
20
20 21 22 23 24 24 26 28
6.
INTERRUPT FUNCTIONS ................................................................................................................
28
7.
STANDBY FUNCTIONS ..................................................................................................................
30
8.
RESET FUNCTION ...........................................................................................................................
31
9.
INSTRUCTION SET .........................................................................................................................
33
10. ELECTRICAL SPECIFICATIONS ......................................................................................................
40
11. CHARACTERISTIC CURVES ...........................................................................................................
53
4
PD75004, 75006, 75008
12. PACKAGE DRAWINGS ...................................................................................................................
58
13. RECOMMENDED SOLDERING CONDITIONS ...............................................................................
61
APPENDIX A. DEVELOPMENT TOOLS ..............................................................................................
62
APPENDIX B. RELATED DOCUMENTS ..............................................................................................
63
5
PD75004, 75006, 75008
1. PIN CONFIGURATION (Top View)
* 42-pin plastic shrink DIP (600 mil)
XT1 XT2 RESET X1 X2 P33 P32 P31 P30 P81 P80 SI/SB1/P03 SO/SB0/P02 SCK/P01 INT4/P00 TI0/P13 INT2/P12 INT1/P11 INT0/P10 NC VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
V SS P40 P41 P42 P43 P50 P51 P52 P53 P60/KR0 P61/KR1 P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P20/PTO0 P21 P22/PCL P23/BUZ
PD75008CU-xxx
PD75006CU-xxx
PD75004CU-xxx
* 44-pin plastic QFP (s 10 mm) s
P20/PTO0 P10/INT0 P11/INT1 P12/INT2
P23/BUZ
P73/KR7
P22/PCL
P21
V DD
NC
P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 P53 P52 P51 P50
1 2 3 4 5 6 7 8 9
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24
NC
P03/TI0 P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P80 P81 P30 P31 P32 P33
PD75004GB-xxx-3B4 PD75006GB-xxx-3B4 PD75008GB-xxx-3B4
10
23 11 12 13 14 15 16 17 18 19 20 21 22
P43
P42
P40
XT1
XT2
RESET
X1
P41
NC
6
V SS
X2
PD75004, 75006, 75008
Pin names P00-P03 : Port 0 P10-P13 : Port 1 P20-P23 : Port 2 P30-P33 : Port 3 P40-P43 : Port 4 P50-P53 : Port 5 P60-P63 : Port 6 P70-P73 : Port 7 P80-P81 : Port 8 KR0-KR7 : Key Return SCK SI : Serial Clock : Serial Input SO SB0,SB1 RESET TI0 PTO0 BUZ PCL INT0, 1, 4 INT2 X1, 2 XT1, 2 NC : Serial Output : Serial Bus 0,1 : Reset Input : Timer Input 0 : Programmable Timer Output 0 : Buzzer Clock : Programmable Clock : External Test Interrupt 0,1,4 : External Test Input 2 : Main System Clock Oscillation 1,2 : Subsystem Clock Oscillation 1,2 : No Connection
7
8
2. BLOCK DIAGRAM
BASIC INTERVAL TIMER INTBT TI0/P13 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 PROGRAM COUNTER * CY ALU SP (8)
PORT 0
4
P00-P03
PORT 1
4
P10-P13
PORT 2 BANK PORT 3
4
P20-P23
BUZ/P23
WATCH TIMER GENERAL REG.
4
P30-P33
INTW
SI/SB1/P03 SO/SB0/P02 SCK/P01
CLOCKED SERIAL INTERFACE INTCSI
PROGRAM MEMORY (ROM) 4096 x 8 BITS PD75004) ( 6016 x 8 BITS (PD75006) 8064 x 8 BITS (PD75008)
PORT 4
4
P40-P43
DECODE AND CONTROL
PORT 5 DATA MEMORY (RAM) 512 x 4 BITS
4
P50-P53
PORT 6
4
P60-P63
INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60 -KR7/P73 CLOCK OUTPUT CONTROL INTERRUPT CONTROL
PORT 7
4
P70-P73
PD75004, 75006, 75008
PORT 8 f X /2 N CLOCK DIVIDER SYSTEM CLOCK GENERATOR SUB MAIN STAND BY CONTROL CPU CLOCK
2
P80-P81
BIT SEQ. BUFFER (16)
PCL/P22
XT1 XT2 X1
X2
V DD
V SS RESET
*: For PD75004, 12 bits. For PD75006 and PD75008, 13 bits.
PD75004, 75006, 75008
3.
3.1
PIN FUNCTIONS
PORT PINS (1/2)
Input/ Output Circuit 1 TYPE* B
Also Served Pin Name Input/Output As
Function
8-Bit I/O
When Reset
P00
Input Input/ Output Input/ Output Input/ Output
INT4
P01 P02
SCK SO/SB0
4-bit input port (PORT0) Pull-up resistors can be specified in 3-bit units for the P01 to P03 pins by software.
F -A X Input F -B
P03 P10 P11 P12 P13 P20 P21 P22 P23 P30* P31*
2
SO/SB1 INT0 With noise elimination function 4-bit input port (PORT1) Internal pull-up resistors can be specified in 4-bit units by software. X Input
M -C
Input
INT1 INT2 TI0 PTO0
B -C
Input/ Output
-- PCL BUZ --
4-bit input/output port (PORT2) Internal pull-up resistors can be specified in 4-bit units by software.
X
Input
E-B
2
P32*2 P33*2
Input/ Output
-- -- --
Programmable 4-bit input/output port (PORT3) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software. N-ch open-drain 4-bit input/output port (PORT4) Internal pull-up resistors can be specified in bit units. (mask option) Resistive voltage is 10 V in the opendrain mode.
X
Input
E-B
P40-43*
2
Input/ Output
--
q Input/ Output N-ch open-drain 4-bit input/output port (PORT5) Internal pull-up resistors can be specified in bit units. (mask option) Resistive voltage is 10 V in the opendrain mode.
High level (with internal pull-up resistor) or high impedance High level (with internal pull-up resistor) or high impedance
M
P50-53*2
--
M
*1: Circles indicate Schmitt trigger inputs. 2: Can directly drive LED.
9
PD75004, 75006, 75008
3.1 PORT PINS (2/2)
Input/ Output Circuit 1 TYPE*
Pin Name Input/Output Also Served As P60 P61 P62 P63 P70 P71 P72 P73 P80 P81 Input/ Output Input/ Output Input/ Output KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 -- --
Function
8-Bit I/O
When Reset
Programmable 4-bit input/output port (PORT6) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software.
Input q
F -A
4-bit input/output port (PORT7) Internal pull-up resistors can be specified in 4-bit units by software.
Input
F -A
2-bit input/output port (PORT8) Internal pull-up resistors can be specified in 2-bit units by software.
X
Input
E-B
*1: Circles indicate Schmitt trigger inputs. 2: Can directly drive LED.
10
PD75004, 75006, 75008
3.2 NON PORT PINS
Input/ Output Circuit TYPE*1 B -C E-B E-B E-B F -A F -B M -C B
Also Served Pin Name Input/Output As TI0 PTO0 PCL BUZ SCK SO/SB0 SI/SB1 INT4 INT0 Input INT1 P11 P13 P20 P22 P23 P01 P02 P03 P00 P10
Functon
When Reset
Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input
Timer/event counter external event pulse Input Timer/event counter output Clock output Fixed frequency output (for buzzer or for trimming the system clock) Serial clock input/output Serial data output Serial bus input/output Serial data input Serial bus input/output Edge detection vector interrupt input (both rising and falling edge detection are effective) Edge detection vector interrupt input (detection edge can be selected) Clock synchronous
Input Input Input Input Input Input Input Input
Input Asynchronous
B -C
INT2
Input
P12
Edge detection testable input (rising edge detection) Asynchronous
Input
B -C
KR0-KR3 KR4-KR7
Input/ Output Input/ Output
P60-P63 P70-P73
Parallel falling edge detection testable input Parallel falling edge detection testable input To connect the crystal/ceramic oscillator to the main system clock generator. When inputting the external clock, input the external clock to pin X1, and the reverse phase of the external clock to pin X2. To connect the crystal oscillator to the subsystem clock generator. When the external clock is used, pin XT1 inputs the external clock. In this case, pin XT2 must be left open. System reset input No connection Positive power supply GND
Input Input
F -A F -A
X1, X2
Input
--
Input
--
XT1 XT2 RESET NC *2 VDD VSS
Input -- -- Input -- -- -- -- -- -- --
Input -- -- -- -- -- -- B -- -- --
*1: Circles indicate Schmitt trigger inputs. 2: When sharing the printed circut board with the PD75P008, the NC pin must be directly connected to VDD.
11
PD75004, 75006, 75008
3.3 PIN INPUT/OUTPUT CIRCUITS
The following shows a simplified input/output circuit diagram for each pin of the PD75008.
TYPE A (for TYPE E-B)
VDD
TYPE D (for TYPE E- B, F- A)
VDD data P-ch
IN output disable
OUT
N-ch
Input buffer of CMOS standard
Push-pull output that can be set in a output high-impedance state (both P-ch and N-ch are off) TYPE E-B
TYPE B
VDD P.U.R. P.U.R. enable P-ch
IN data Type D output disable IN/OUT
Type A
Schmitt trigger input with hysteresis characteristics
P.U.R. : Pull-Up Resistor
TYPE B-C
TYPE F-A
VDD P.U.R. P.U.R. enable P-ch
VDD P.U.R. P-ch P.U.R. enable
data Type D output disable
IN/OUT
IN
Type B
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
12
PD75004, 75006, 75008
TYPE F-B
VDD P.U.R. P.U.R. enable VDD P-ch P-ch
TYPE M-C
VDD P.U.R. P.U.R. enable IN/OUT data P-ch IN/OUT N-ch
output disable (P) data output disable
N-ch output disable (N) output disable
P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor TYPE M
VDD P.U.R. enable (Mask option) data output disable
IN/OUT
N-ch
(withstand voltage: +10 V)
Middle voltage input buffer (withstand voltage: +10 V) P.U.R. : Pull-Up Resistor
13
PD75004, 75006, 75008
3.4 SELECTION OF MASK OPTION
The following mask operations are available and can be specified for each pin.
Table 3-1 Mask Option Selection
Pin P40-P43, P50-P53 Mask Option * With pull-up resistor * Without pull-up resistor
*: Mask option can be specified in bit units.
5
3.5
RECOMMENDED PROCESSING OF UNUSED PINS
Table 3-2 Processing of Unused Pins
Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80-P81 XT1 XT2
Recommended Connections Connect to VSS
Connect to VSS or VDD
Connect to VSS
Input : Connect to VSS or VDD Output: Open
Connect to VSS or VDD Open
14
PD75004, 75006, 75008
3.6 NOTES ON USING THE P00/INT4, AND RESET PINS 5
In addition to the functions described in Sections 3.1 PORT PINS and 3.2 NON PORT PINS, an exclusive function for setting the test mode, in which the internal fuctions of the PD75008 are tested (solely used for IC tests), is provided to the P00/INT4 and RESET pins. If a voltage exceeding VDD is applied to either of these pins, the PD75008 is put into test mode. Therefore, even when the PD75008 is in normal operation, if noise exceeding the VDD is input into any of these pins, the
PD75008 will enter the test mode, and this will cause problems for normal operation.
As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up and the above montioned problem may occur. Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot be avoided, suppress the noise using a capacitor or diode as shown in the figure below. * Connect a diode having a low VF across P00/INT4 and RESET, and VDD. (0.3 V max.)
VDD
* Connect a capacitor across P00/INT4 and RESET, and VDD.
VDD
Low VF diode P00/INT4, RESET
VDD
VDD
P00/INT4, RESET
15
PD75004, 75006, 75008
4. MEMORY CONFIGURATION * Program memory (ROM) ... 4096 x 8 bits (0000H-0FFFH) : PD75004 ... 6016 x 8 bits (0000H-177FH) : PD75006 ... 8064 x 8 bits (0000H-1F7FH) : PD75008 * 0000H-0001H : Vector table to which address from which program is started is written after reset * 0002H-000BH: Vector table to which address from which program is started is written after interrupt * 0020H-007FH : Table area referenced by GETI instruction * Data memory (RAM) * Data area .... 512 x 4 bits (000H-1FFH) * Peripheral hardware area .... 128 x 4 bits (F80H-FFFH)
Address 7 000H MBE 6 0 5 0 4 0 Internal reset start address (upper 4 bits) Internal reset start address (lower 8 bits) 002H MBE 0 0 0 INTBT/INT4 start address (upper 4 bits) INTBT/INT4 start address (lower 8 bits) 004H MBE 0 0 0 INT0 start address (upper 4 bits) INT0 start address (lower 8 bits) 006H MBE 0 0 0 INT1 start address (upper 4 bits) INT1 start address (lower 8 bits) 008H MBE 0 0 0 INTCSI start address (upper 4 bits) INTCSI start address (lower 8 bits) 00AH MBE 0 0 0 INTT0 start address (upper 4 bits) INTT0 start address (lower 8 bits) BRCD ! caddr instruction branch address CALLF !faddr instruction entry address 0
CALL ! addr instruction subroutine entry address
020H GETI instruction reference table 07FH 080H
BR $addr instruction relational branch address (-15 to -1, +2 to +16)
7FFH 800H
Branch destination address and subroutine entry address for GETI instruction
FFFH
Fig. 4-1 Program Memory Map (PD75004)
16
PD75004, 75006, 75008
Address 7 0000H MBE 6 0 5 0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits) 0002H MBE 0 0 INTBT/INT4 start address (upper 5 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE 0 0 INT0 start address (upper 5 bits) INT0 start address (lower 8 bits) 0006H MBE 0 0 INT1 start address (upper 5 bits) INT1 start address (lower 8 bits) 0008H MBE 0 0 INTCSI start address (upper 5 bits) INTCSI start address (lower 8 bits) 000AH MBE 0 0 INTT0 start address (upper 5 bits) INTT0 start address (lower 8 bits) CALLF ! faddr instruction entry address 0
CALL ! addr instruction subroutine entry address
BRCB ! caddr BR ! addr instruction instruction branch branch address address
0020H GETI instruction reference table 007FH 0080H BR $addr instruction relational branch address (-15 to -1, +2 to +16)
07FFH 0800H
Branch destination address and subroutine entry address for GETI instruction
0FFFH 1000H BRCB ! caddr instruction branch address 177FH
Fig. 4-2 Program Memory Map (PD75006)
17
PD75004, 75006, 75008
Address 7 0000H MBE 6 0 5 0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits) 0002H MBE 0 0 INTBT/INT4 start address (upper 5 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE 0 0 INT0 start address (upper 5 bits) INT0 start address (lower 8 bits) 0006H MBE 0 0 INT1 start address (upper 5 bits) INT1 start address (lower 8 bits) 0008H MBE 0 0 INTCSI start address (upper 5 bits) INTCSI start address (lower 8 bits) 000AH MBE 0 0 INTT0 start address (upper 5 bits) INTT0 start address (lower 8 bits) CALLF ! faddr instruction entry address 0
CALL ! addr instruction subroutine entry address
BRCB ! caddr BR ! addr instruction instruction branch branch address address
0020H GETI instruction reference table 007FH 0080H BR $addr instruction relational branch address (-15 to -1, +2 to +16)
07FFH 0800H
Branch destination address and subroutine entry address for GETI instruction
0FFFH 1000H BRCB ! caddr instruction branch address 1F7FH
Fig. 4-3 Program Memory Map (PD75008)
18
PD75004, 75006, 75008
Data memory General-purpose register area Stack area 000H 007H 008H 256x 4 (248 x 4) Data area Static RAM (512 x 4) 0FFH 100H (8 x 4)
Memory bank
0
256x 4
1
1FFH Not provided F80H 128x 4 FFFH 15
Peripheral hardware area
Fig. 4-4 Data Memory Map
19
PD75004, 75006, 75008
5.
5.1
PERIPHERAL HARDWARE FUNCTIONS
PORTS : : 8 8
I/O ports are classified into the following 3 kinds: * CMOS input (PORT0, 1) * N-ch open-drain input/output (PORT4, 5) Total * CMOS input/output (PORT2, 3, 6, 7, and 8) : 18 : 34
Table 5-1 Port Function
Port Name (Symbol) PORT0 PORT1 PORT3* PORT6 4-bit input/output PORT2 PORT7 Can be set in input or output mode in 1-bit units. Function 4-bit input Operation and Feature Can be always read or tested regardless of operation mode of multiplexed pin. Remarks Multiplexed with SO/SB0, SI/SB1, SCK, INT0-2, 4, and TIO Port 6 is multiplexed with KR0 to KR3.
Port 2 is multiplexed with PTO0, PCL, and BUZ.
Can be set in input or output mode in 4-bit units. Ports 6 and 7 are used in pairs to input/output data in 8-bit units.
Port 7 is multiplexed with KR4-KR7. Can be connected to a pull-up resistor in 1-bit units by using mask option. --
PORT4* PORT5*
4-bit input/output (N-ch open-drain, 10 V) 2-bit input/output
Can be set in input or output mode in 4-bit units. Ports 4 and 5 are used in pairs to input/output data in 8-bit units. Can be set input or output mode in 2-bit units.
PORT8
*: Can directly drive LED.
20
PD75004, 75006, 75008
5.2 CLOCK GENERATOR CIRCUIT
The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and system clock control register (SCC). This circuit can generate two types of clocks: main system clock and subsystem clock. In addition, it can also change the instruction execution time. * 0.95 s, 1.91 s, 15.3 s (main system clock: 4.19 MHz) * 122 s (subsystem clock: 32.768 kHz) 5
XT1 XT2 X1 X2 Main system f X clock oscillator 1/8 to 1/4096 Frequency divider 1/2 1/16 Subsystem clock oscillator f XT Watch timer * Basic interval timer (BT) * Timer/event counter * Serial interface * Watch timer * INT0 noise rejecter circuit * Clock output circuit
SCC3
Internal bus
Oscillator disable signal
Selector
WM.3 SCC
Selector
Frequency divider 1/4 * CPU * INT0 noise rejecter circuit * Clock output circuit
SCC0 PCC PCC0 PCC1 4 PCC2 HALT* STOP* PCC3 R Q HALT F/F S
PCC2, PCC3 clear signal
STOP F/F Q S R
Wait release signal from BT RESET signal Standby release signal from interrupt control circuit
*: instruction execution. Remarks 1: fX = Main system clock frequency 2: fXT = Subsystem clock frequency 3: = CPU clock 4: PCC: Processor clock control register 5: SCC: System clock control register 6: One clock cysle (tCY) of is one machine cycle of an instruction. For tCY, refer to AC characteristics in 10. ELECTRICAL SPECIFICATIONS.
Fig. 5-1 Clock Generator Block Diagram
21
PD75004, 75006, 75008
5.3 CLOCK OUTPUT CIRCUIT
The clock output circuit outputs clock pulse from the P22/PCL pin. This clock output circuit is used to output clock pulses to the remote control output, peripheral LSIs, etc. * Clock output (PCL) : , 524, 262, 65.5 kHz (operating at 4.19 MHz) * Buzzer output (BUZ) : 2 kHz (operating at 4.19 MHz, or 32.768 kHz) Fig. 5-2 shows the clock output circuit configuration.
From the clock generator fX/23 Selector fX/24 fX/26 PCL/P22 Output buffer
PORT2.2 CLOM3 CLOM2 CLOM1 CLOM0 CLOM
P22 output latch
Bit 2 of PMGB
Port 2 input/ output mode specification bit
4 Internal bus
Fig. 5-2 Clock Output Circuit Configuration
Remarks:
A measures to prevent outputting narrow width pulse when selecting clock output enable/ disable is taken.
22
PD75004, 75006, 75008
5.4 BASIC INTERVAL TIMER
The basic interval timer has these functions: * Interval timer operation which generates a reference time interrupt * Watchdog timer application which detects a program runaway * Selects the wait time for releasing the standby mode and counts the wait time * Reads out the count value
From the clock generator Clear fX/25 Clear
fX/27 MPX fX/29 BT Basic interval timer (8-bit frequency divider circuit)
Set signal
BT interrupt request flag
fX/212
Vector interrupt request IRQBT signal
3
Wait release signal for standby release BTM0 BTM
BTM3
BTM2
BTM1
SET1*
4 Internal bus
8
Remarks : *: Instruction execution
Fig. 5-3 Basic Interval Timer Configuration
23
PD75004, 75006, 75008
5.5 WATCH TIMER
The PD75008 has a built-in 1-ch watch timer. The watch timer is configured as shown in Fig. 5-4. * Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by IRQW. * 0.5 second interval can be generated either from the main system clock or subsystem clock. * Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is convenient for program debugging, test, etc. * Fixed frequency (2.048 kHz) can be output to the P23/BUZ pin. This can be used for beep and system clock frequency trimming. * The frequency divider circuit can be cleared so that zero second watch start is possible.
fW (256 Hz: 3.91 ms) 27 fX 128 From the (32.768 kHz) clock generator f XT (32.768 kHz) fW 2 14 (2 Hz 0.5 sec) Selector INTW (IRQW set signal)
Selector
fW (32.768 kHz)
Frequency divider
f W (2.048 16 kHz)
Clear Output buffer P23/BUZ
WM WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0 Bit test instruction Internal bus
PORT2.3
P23 output latch
Bit 2 of PMGB
Port 2 input/output mode
8
( ) is for fX = 4.194304 MHz, fXT = 32.768 kHz.
Fig. 5-4 Watch Timer Block Diagram
5.6 TIMER/EVENT COUNTER The timer/even counter has these functions:
The PD75008 has a built-in 1-ch timer/event counter. * Programmable interval timer operation
* Outputs square-wave signal of an arbitrary frequency to the PTO0 pin. * Event counter operation * Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation). * Supplies serial shift clock to the serial interface circuit. * Count condition read out function
24
Internal bus 8 SET1*1 TM0 8 8 TMOD0 TOE0 TO enable flag Coincidence PORT2.0 P20 output latch Bit 2 of PGMB
Port 2 input/ output mode
TM07 TM06 TM05 TM04 TM03 TM02 TM01 TM00
Modulo register (8)
PORT1.3
8 Comparator (8)
To serial interface
TOUT F/F Reset Output buffer
P20/PTO0
Input buffer P13/TI0 From * the clock generator
2
8 T0 MPX Count register (8) CP Clear Timer operation start signal
(
INTT0 IRQT0 set signal
)
PD75004, 75006, 75008
RESET IRQT0 clear signal *1: SET1: Instruction execution *2: Refer to Fig. 5-1.
Fig. 5-5 Timer/Event Counter Block Diagram
25
PD75004, 75006, 75008
5.7 SERIAL INTERFACE The PD75008 is equipped with a serial interface that operates in the following modes: * Three-line serial I/O mode (MSB/LSB first selectable) * Two-line serial I/O mode (MSB first) * SBI mode (MSB first) In the three-line I/O mode, the microcomputer can be connected to a microcomputer in the 75X series or 78K series devices, or various I/O devices. In the two-line serial mode and SBI mode, communication can be established with two or more devices.
26
Internal bus
8/4
Bit test 8 8
8
Slave address register (SVA)
Bit manipulation (8) RELT CMDT
SET CLR
Bit test SBIC
CSIM
Coincidence signal Address comparator (8) P03/SI/SB1
SO latch
Selector
Shift register (SIO)
(8)
D
Q
P02/SO/SB0
Selector
Busy/ acknowledge output circuit
Bus release/ command/ acknowledge detector circuit P01/SCK
RELD CMDD ACKD
ACKT ACKE BSYE
Serial clock counter P01 output latch
INTCSI control circuit
(
Serial clock selector
INTCSI IRQCSI set signal
)
PD75004, 75006, 75008
Serial clock control circuit
fX/23 fX/24 fX/26 TOUT F/F (from timer/ event counter) External SCK
Fig. 5-6 Serial Interface Block Diagram
27
PD75004, 75006, 75008
5.8 BIT SEQUENTIAL BUFFER .... 16 BITS
The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units.
Address bit 3 Symbol
FC3H 2 BSB3 1 0 3
FC2H 2 BSB2 1 0 3
FC1H 2 BSB1 1 0 3
FC0H 2 BSB0 1 0
L register
L=F
L=C L=B INCS L
L=8 L=7 DECS L
L=4 L=3
L=0
Remarks:
For the pmem.@L addressing, the specification bit is shifted according to the L register.
Fig. 5-7 Bit Sequential Buffer Format
6. INTERRUPT FUNCTIONS
The PD75008 has 8 different interrupt sources and multiplexed interrupt through the software control. In addition to that, the PD75008 is also provided with two types of edge detection testable inputs. The interrupt control circuit of the PD75008 has these functions: * Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt flag (IExxx) and interrupt master enable flag (IME). * The interrupt start address can be arbitrarily set. * Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of software). * Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).
28
Internal bus 2 IM2 1 IM1 3 IM0 Interrupt enable flag (IE xxx ) IME IST0
INT BT INT4 /P00 INT0 /P10 INT1 /P11 Both edge delection circuit Edge Noise delection elimination circuit circuit Edge delection circuit INTCSI INTT0
IRQBT IRQ4 IRQ0 IRQ1 IRQCSI IRQT0 IRQW VRQn
Decoder
Priority control circuit
Vector table address generator
INTW
Selector
INT2 /P12
Rising edge delection circuit Falling edge delection circuit
PD75004, 75006, 75008
IRQ2 Standby release signal
KR0/P60 KR7/P73
IM2
Fig. 6-1 Interrupt Control Block Diagram
29
PD75004, 75006, 75008
7. STANDBY FUNCTIONS
The PD75008 has two different standby modes (STOP mode and HALT mode) to reduce the power consumption while waiting for program execution.
Table 7-1 Each Status in Standby Mode
STOP Mode Setting Instruction System Clock for Setting Operation Status Clock Generator Basic Interval Timer Serial Interface STOP instrtuction Can be set only when operating on the main system clock Only the main system clock stops its operation. No operation
HALT Mode HALT instruction Can be set either with the main system clock or the subsystem clock Only the CPU clock stops its operation. (oscillation continues) Can operate only when main system clock oscillates (Sets IRQBT at reference time interval) Can operate only when external SCK input is selected as serial clock, or when main system clock oscillates Can operate only when TI0 pin input is selected as count clock, or when main system clock oscillates Can operate
Can operate only when the external SCK input is selected for the serial clock Can operate only when the TI0 pin input is selected for the count clock Can operate when fXT is selected as the count clock INT1, INT2, and INT4 can operate. Only INT0 can not operate. No operation An interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the RESET signal input
Timer/Event Counter Watch Timer External Interrupt CPU Release Signal
An interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the RESET signal input
30
PD75004, 75006, 75008
8. RESET FUNCTION
When the RESET signal is input, the PD75008 is reset and each hardware is initialized as indicated in Table 8-1. Fig. 8-1 shows the reset operation timing.
Wait (31.3ms/4.19MHz) RESET input
Operation mode or standby mode
HALT mode
Operation mode
Internal reset operation
Fig. 8-1 Reset Operation by RESET Input
Table 8-1 Status of Each Hardware after Reset (1/2)
Hardware Program Counter (PC) RESET Input in Standby Mode The contents of the lower 4 bits of address 000H of the program memory are set to PC11-8, and the contents of address 001H are set to PC7-0. Retained 0 0 The contents of bit 7 of address 000H of the program memory is set to MBE. Undefined Retained * Retained 0 Undefined 0 0 FFH 0 0, 0 0 RESET Input during Operation
Same as at left
PSW
Carry Flag (CY) Skip Flag (SK0-2) Interrupt Status Flag (IST0) Bank Enable Flag (MBE)
Undefined 0 0 Same as at left Undefined Undefined Undefined 0 Undefined 0 0 FFH 0 0, 0 0
Stack Pointer (SP) Data Memory (RAM) General-Purpose Register (X, A, H, L, D, E, B, C) Bank Selection Register (MBS) Basic Interval Counter (BT) Timer Mode Register (BTM) Timer/Event Counter Counter (T0) Module Register (TMOD0) Mode Register (TM0) TOE0, TOUT F/F Watch Timer Mode Register (WM)
*: Data of address 0F8H to 0FDH of the data memory becomes undefined when a RESET signal is input.
31
PD75004, 75006, 75008
Table 8-1 Status of Each Hardware after Reset (2/2)
Hardware Serial Interface Shift Register (SIO) Operation Mode Register (CSIM) SBI Control Register (SBIC) Slave Address Register (SVA) Clock Generator, Clock Output Circuit Processor Clock Control Register (PCC) System Clock Control Register (SCC) Clock Output Mode Register (CLOM) Interrupt Function Interrupt Enable Flag (IExxx) Interrupt Master Enable Flag (IME) INT0, INT1, INT2 Mode Registers (IM0, 1, 2) Digital Port Output Buffer Output Latch Input/Output Mode Register (PMGA, B, C) Pull-Up Resistor Specification Register (POGA, B) Bit sequential buffer (BSB0-3) RESET Input in Standby Mode Retained 0 0 Retained 0 0 0 0 0 0, 0, 0 Off Clear (0) 0 0 RESET Input during Operation Undefined 0 0 Undefined 0 0 0 0 0 0, 0, 0 Off Clear (0) 0 0
Retained
Specified
32
PD75004, 75006, 75008
9. INSTRUCTION SET
(1) Operand representation and description Describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to RA75X Assembler Package User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from several operands. The uppercase characters, +, and - are keywords and must be described as is. Describe an appropriate numeric value or label as immediate data. The symbols in the register and flag symbols can be described as labels in the places of mem, fmem, pmem, and bit (for details, refer to PD7500X Series User`s Manual (IEM-5033)). However, fmem and pmem restricts the label that can be described.
Representation reg reg1 rp rp1 rp2 rpa rpa1 n4 n8 mem* bit fmem pmem addr caddr faddr taddr PORTn IExxx MBn Description X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE HL, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label 2-bit immediate data or label FB0H to FBFH,FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label
PD75004 PD75006 PD75008
0000H to 0FFFH immediate data or label 0000H to 177FH immediate data or label 0000H to 1F7FH immediate data or label
12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (where bit0 = 0) or label PORT0 to PORT8 IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW MB0, MB1, MB15
*: Only even address can be described as mem for 8-bit data processing.
33
PD75004, 75006, 75008
(2) A B C D E H L X XA BC DE HL PC SP CY PSW MBE IME IExxx MBS PCC . (xx) xxH Legend of operation field : A register; 4-bit accumulator : B register; 4-bit accumulator : C register; 4-bit accumulator : D register; 4-bit accumulator : E register; 4-bit accumulator : H register; 4-bit accumulator : L register; 4-bit accumulator : X register; 4-bit accumulator : Register pair (XA); 8-bit accumulator : Register pair (BC); 8-bit accumulator : Register pair (DE); 8-bit accumulator : Register pair (HL); 8-bit accumulator : Program counter : Stack pointer : Carry flag; or bit accumulator : Program status word : Memory bank enable flag : Interrupt mask enable flag : Interrupt enable flag : Memory bank selector register : Processor clock control register : Delimiter of address and bit : Contents addressed by xx : Hexadecimal data
PORTn : Port n (n = 0 to 8)
34
PD75004, 75006, 75008
(3) Symbols in addressing area field
*1 *2 *3 MB = MBE . MBS (MBS = 0, 1, 15) MB = 0 MBE = 0 : MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH addr = 000H-FFFH (PD75004) 0000H-177FH (PD75006) 0000H-1F7FH (PD75008) addr = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 caddr = 000H-FFFH (PD75004) 0000H-0FFFH (PC12 = 0 : PD75006, 75008) 0000H-177FH (PC12 = 1 : PD75006) 0000H-1F7FH (PC12 = 1 : PD75008) faddr = 0000H-07FFH taddr = 0020H-007FH Program memory addressing Data memory addressing
*4 *5 *6
*7 *8
*9 *10
Remarks 1: 2: 3: 4: (4)
MB indicates memory bank that can be accessed. In *2, MB = 0 regardless of MBE and MBS. In *4 and *5, MB = 15 regardless of MBE and MBS. *6 to *10 indicate areas that can be addressed.
Machine cycle field In this field, S indicates the number of machine cycles required when an instruction having a skip
function skips. The value of S varies as follows: * When no instruction is skipped ........................................................................ * When 1-byte or 2-byte instruction is skipped ................................................. * When 3-byte instruction (BR ! addr or CALL ! addr) is skipped .................. S=0 S=1 S=2
Note : The GETI instruction is skipped in one machine cycle.
One machine cycle equals to one cycle of the CPU clock , (=tCY), and can be changed in three steps depending on the setting of the processor clock control register (PCC).
35
PD75004, 75006, 75008
Machine Bytes Cycles 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 1 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 3 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp reg1 A rp1 XA A (HL) A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp * PD75004 XA (PC11-8+DE)ROM * PD75006, 75008 XA (PC12-8+DE)ROM XA, @PCXA 1 3 * PD75004 XA (PC11-8+XA)ROM * PD75006, 75008 XA (PC12-8+XA)ROM Arithmetic Operation ADDC SUBS SUBC AND OR XOR Accumu- RORC lator ManipuNOT lation ADDS A, #n4 A, @HL A, @HL A, @HL A, @HL A, #n4 A, @HL A, #n4 A, @HL A, #n4 A, @HL A A 1 1 1 1 1 2 1 2 1 2 1 1 2 1+S 1+S 1 1+S 1 2 1 2 1 2 1 1 2 A A+n4 A A+(HL) A, CY A+(HL)+CY A A-(HL) A, CY A-(HL)-CY A A n4 A A (HL) A A n4 A A (HL) A A n4 A A (HL) CY A0, A3 CY, An-1 An AA *1 *1 *1 *1 *1 *1 *1 borrow carry carry *1 *2 *1 *3 *3 *1 *2 *1 *1 *1 *3 *3 *3 *3 String effect A String effect B Addressing Area
Instructions
Mnemonics
Operand
Operation
Skip Conditions String effect A
Transfer MOV
A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @rpa1 XA, @HL @HL, A @HL, XA A,mem XA, mem mem, A mem, XA A, reg XA, rp reg1, A rp1, XA
XCH
A, @HL A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp
MOVT
XA, @PCDE
36
PD75004, 75006, 75008
Machine Bytes Cycles 1 2 2 1 2 2 1 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1+S 2+S 2+S 1+S 2+S 2+S 1+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 Addressing Area *1 *3
Instructions Increment/ Decrement
Mnemonics INCS
Operand
Operation reg reg+1 (HL) (HL)+1 (mem) (mem)+1 reg reg-1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if A = reg CY 1 CY 0 Skip if CY = 1 CY CY (mem.bit) 1
(fmem.bit) 1
Skip Conditions reg = 0 (HL) = 0 (mem) = 0 reg = FH reg = n4 *1 (HL) = n4
reg @HL mem
DECS
reg reg, #n4 @HL, #n4 A, @HL A, reg
Compare SKE
*1
A = (HL) A = reg
Carry flag lation Bit Manipulation
SET1 CLR1 NOT1
CY CY CY CY mem.bit fmem.bit pmem.@L @H+mem.bit
Manipu- SKT Memory/ SET1
CY = 1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H+mem.bit) = 0 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1
(pmem7-2 + L3-2.bit(L1-0)) 1 (H + mem3-0.bit) 1
(mem.bit) 0 (fmem.bit) 0
CLR1
mem.bit fmem.bit pmem.@L @H+mem.bit
(pmem7-2 + L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1
Skip if (pmem7-2+L3-2.bit (L1-0)) = 1
SKT
mem.bit fmem.bit pmem.@L @H+mem.bit
Skip if (H + mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2 +L3-2.bit (L1-0)) = 0 Skip if (H + mem3-0.bit) = 0
Skip if (fmem.bit) = 1 and clear
SKF
mem.bit fmem.bit pmem.@L @H+mem.bit
SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit OR1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit XOR1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit
Skip if (pmem7-2+L3-2.bit (L1-0)) = 1 and clear
Skip if (H+mem3-0.bit) = 1 and clear
CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit (L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit)
CY CY (pmem7-2+L3-2.bit (L1-0))
CY CY (H+mem3-0.bit)
37
PD75004, 75006, 75008
Machine Bytes Cycles -- -- Addressing Area *6
Instructions Branch
Mnemonics BR
Operand
Operation * PD75004 PC11-0 addr (The most suitable instruction is selectable from among BRCB !caddr, and BR $addr depending on the assembler.) * PD75006, 75008 PC12-0 addr (The most suitable instruction is selectable from among BR !addr, BRCB !caddr, and BR $addr depending on the assembler.)
Skip Conditions
addr
!addr $addr
3 1
3 2
* PD75006, 75008 PC12-0 addr * PD75004 PC11-0 addr * PD75006, 75008 PC12-0 addr
*6 *7
BRCB
!caddr
2
2
* PD75004 PC11-0 caddr11-0 * PD75006, 75008 PC12-0 PC12 + caddr11-0
*8
Subroutine/ Stack Control
CALL
!addr
3
3
* PD75004 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, 0, 0, 0 PC11-0 addr, SP SP-4 * PD75006, 75008 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, 0, 0, PC12 PC12-0 addr, SP SP-4
*6
CALLF
!faddr
2
2
* PD75004 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, 0, 0, 0 PC11-0 0, faddr, SP SP-4 * PD75006, 75008 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, 0, 0, PC12 PC12-0 0, 0, faddr, SP SP-4
*9
RET
1
3
* PD75004 MBE, x, x, x (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4 * PD75006, 75008 MBE, x, x, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4
RETS
1
3+S
* PD75004 MBE, x, x, x (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4, then skip unconditionally * PD75006, 75008 MBE, x, x, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4, then skip unconditionally
Undefined
38
PD75004, 75006, 75008
Machine Bytes Cycles 1 3 Addressing Area
Instructions Subroutine/ Stack Control (Cont`d)
Mnemonics RETI
Operand
Operation * PD75004 MBE, x, x, x (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 * PD75006, 75008 MBE, x, x, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6
Skip Conditions
PUSH POP Interrupt Control I/O DI EI
rp BS rp BS IExxx IExxx
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 3
(SP-1)(SP-2) rp, SP SP-2 (SP-1) MBS, (SP-2) 0, SP SP-2 rp (SP+1)(SP), SP SP+2 MBS (SP+1), SP SP+2 IME 1 IExxx 1 IME 0 IExxx 0 A PORTn XA PORTn+1,PORTn PORTn A PORTn+1, PORTn XA
(n = 0-8) (n = 4, 6) (n = 2-8) (n = 4, 6)
IN
*
A, PORTn XA, PORTn PORTn, A PORTn, XA
OUT * CPU Control Special HALT STOP NOP SEL GETI
Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation MBS n (n = 0, 1, 15) * PD75004 Where TBR instruction, PC11-0 (taddr)3-0+(taddr+1) ......................................................... Where TCALL instruction, (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, 0, 0, 0 PC11-0 (taddr)3-0+(taddr+1) SP SP-4 ......................................................... Except for TBR and TCALL instructions, Instruction execution of (taddr)(taddr+1) * PD75006, 75008 Where TBR instruction, PC12-0 (taddr)4-0+(taddr+1) ......................................................... Where TCALL instruction, (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, 0, 0, PC12 PC12-0 (taddr)4-0+(taddr+1) SP SP-4 ......................................................... Except for TBR and TCALL instructions, Instruction execution of (taddr)(taddr+1) *10 .............................
MBn taddr
2 1
............................. Depends on referenced instruction
.............................
............................. Depends on referenced instruction
*: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15.
39
PD75004, 75006, 75008
10. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25C)
Parameter Supply Voltage Input Voltage Symbol VDD VI1 VI2 Other than ports 4, 5 Ports 4, 5 w/pull-up resistor Open drain Output Voltage High-Level Output Current Low-Level Output Current VO IOH IOL* 1 pin All pins Ports 0, 3, 4, 5 1 pin Other than ports 0, 3, 4, 5 1 pin Total of ports 0, 3, 4, 5, 8 Total of ports 2, 6, 7 Operating Temperature Storage Temperature Topt Tstg Peak rms Peak rms Peak rms Peak rms Conditions Ratings -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to +11 -0.3 to VDD+0.3 -10 -30 30 15 20 10 160 120 66 33 -40 to +85 -65 to +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA C C
*: rms = Peak value x Duty
CAPACITANCE (Ta = 25C, VDD = 0 V)
Parameter Input Capacitance Output Capacitance Input/Output Capacitance Symbol CIN COUT CIO f = 1 MHz Pins other than thosemeasured are at 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
40
PD75004, 75006, 75008
MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V)
Recommended Constants
Oscillator Ceramic
Item Oscillation frequency(fXX)* 1
Conditions VDD = Oscillation voltage range
MIN. 1.0
TYP.
MAX. 5.0 *
3
Unit MHz
X1 C1
X2 C2
Oscillation stabiliza- After VDD come to tion time*2 MIN. of oscillation voltage range
4
ms
Crystal
X1 C1 X2 C2
Oscillation frequency (fXX)* 1 Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2
1.0
4.19
5.0 * 10 30
3
MHz ms ms
External Clock
X1 X2
X1 input frequency (fX)*1 X1 input high-, low-level widths (tXH, tXL)
1.0
5.0 *3
MHz
PD74HCU04
100
500
ns
*1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after VDD has been applied or the STOP mode has been released. 3: When the oscillation frequency is 4.19 MHz < fx 5.0 MHz, do not select PCC = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 s, falling short of the rated minimum value of 0.95 s. 5 Note: When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. * Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the osccillator circuit at the same potential as VSS. Do not connect the ground pattern through which a high current flows. * Do not extract signals from the oscillation circuit. 5
41
PD75004, 75006, 75008
SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V)
Recommended Constants
Oscillator Crystal
Item Oscillation frequency (fXT)*1
Conditions
MIN. 32
TYP. 32.768 1.0
MAX. 35 2 10
Unit kHz s s
XT1
XT2 R
Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2
C3
C4
External Clock
XT1 Open XT2
XT1 input frequency (fXT)*1 XT1 input high-, low-level widths (tXTH, tXTL)
32
100
kHz
5
15
s
*1: Express the characteristcs of the oscillator circuit. 2: Time required for oscillator to stabilize after VDD has been applied. 5 Note: When using the oscillation circuit of the subsystem clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. * Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VSS. Do not connect the ground pattern through which a high current flows. * Do not extract signals from the oscillation circuit. The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. When using the subsystem clock, therefore, exercise utmost care in wiring the circuit.
42
PD75004, 75006, 75008
RECOMMENDED OSCILLATION CIRCUIT CONSTANTS MAIN SYSTEM CLOCK: CERAMIC OSCILLATOR (Ta = -40 to +85C)
Manufacturer Murata Mfg. Frequency (MHz) 1.00 to 1.99 2.00 to 2.44 CST x.xxMG093* CSA x.xxMGU* CST x.xxMGU* CSA x.xxMG* 2.00 to 5.00 CST x.xxMG* Kyoto Ceramic KBR-1000H KBR-2.0MS KBR-4.0MS KBR-5.0M Toko CRHB4.00M 1.00 2.00 4.00 5.00 4.00 -- 100 47 33 33 27 -- 100 47 33 33 27 3.0 2.7 2.7 2.7 3.0 3.0 6.0 2.45 to 5.00 -- 30 -- 30 -- 30 -- 30 2.7 2.7 2.7 3.0 6.0 Recommended Circuit Constants C1 (pF) 30 30 C2 (pF) 30 30 Operating Voltage Range MIN. (V) 2.7 2.7 MAX. (V)
Product Name
CSA x.xxMK* CSA x.xxMG093*
*: x.xx indicates frequency.
MAIN SYSTEM CLOCK: XTAL (Ta = -20 to +70C)
Manufacturer Kinseki Frequency (MHz) 1.0 to 2.0 2.0 to 5.0 20 * 22 2.7 6.0 Recommended Circuit Constants C1 (pF) C2 (pF) Operating Voltage Range MIN. (V) MAX. (V)
Product Name
HC-6U HC-18U HC-43U, 49/U
*: Adjust the oscillation frequency in a range of C1 = 15 to 33 pF.
SUBSYSTEM CLOCK: XTAL (Ta = -10 to +60C)
Manufacturer Kinseki Frequency (MHz) 32.768 Recommended Circuit Constants C3 (pF) 18 * C4 (pF) 18 R (k) 330 Operating Voltage Range MIN. (V) 2.7 MAX. (V) 6.0
Product Name
P-3
*: Adjust the oscillation frequency in a range of C3 = 10 to 33 pF.
43
PD75004, 75006, 75008
DC CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V)
Parameter High-Level Input Voltage Symbol VIH1 VIH2 VIH3 VIH4 Low-level Input Voltage VIL1 VIL2 VIL3 High-Level Output Voltage Low-Level Output Voltage VOH1 Ports 2, 3, 8 Ports 0, 1, 6, 7, RESET Ports 4, 5 X1, X2, XT1 Ports 2, 3, 4, 5, 8 Ports 0, 1, 6, 7, RESET X1, X2, XT1 Ports 0, 2, 3, 6, 7, 8 Ports 0, 2, 3, 4, 5, 6, 7, 8 VDD = 4.5 to 6.0 V, IOH = -1 mA IOH = -100 A VOL1 Ports 4 and 5 VDD = 4.5 to 6.0 V IOL = 15 mA Ports 3 VDD = 4.5 to 6.0 V IOL = 15 mA VDD = 4.5 to 6.0 V IOL = 1.6 mA IOL = 400 A VOL2 High-Level Input Leakage Current ILIH1 ILIH2 ILIH3 Low-Level Input Leakage Current High-Level Output Leakage Current Low-Level Output Leakage Current ILIL1 ILIL2 ILOH1 ILOH2 ILOL VOUT = VDD VOUT = 10 V VOUT = 0 V Ports 0, 1, 2, 3, 6, 7, 8 VDD = 5.0 V10% (except P00) VIN = 0V VDD = 3.0 V10% Ports 4, 5 VOUT = VDD-2.0 V VDD = 5.0 V10% VDD = 3.0 V10% 15 30 15 10 40 40 VIN = 10 V VIN = 0 V SB0, 1 Open-drain VIN = VDD Pull-up 1 k VDD = 4.5 to 6.0 V Pull-up 5 k Other than below X1, X2, XT1 Ports 4, 5 (open-drain) Other than below X1, X2, XT1 Other than below Ports 4, 5 (open-drain) w/pull-up resistor Open-drain Conditions MIN. 0.7VDD 0.8VDD 0.7VDD 0.7VDD VDD-0.5 0 0 0 VDD-1.0 VDD-0.5 0.4 2.0 TYP. MAX. VDD VDD VDD 10 VDD 0.3VDD 0.2VDD 0.4 Unit V V V V V V V V V V V
0.6
2.0
V
0.4 0.5 0.2VDD 0.2VDD 3 20 20 -3 -20 3 20 -3 80 300 70 60
V V V V
A A A A A A A A
k k k k
Internal Pull-Up Resistor RL1 RL2
....
44
PD75004, 75006, 75008
Parameter
Symbol 4.19 MHz*4 crystal oscillator IDD2 IDD3 IDD4 IDD5 C1 = C2 = 22pF 32.768 kHz*5 crystal oscillator XT1 = 0 V STOP mode
Conditions VDD = 5.0 V10%* 2 VDD = 3.0 V10%* 3 HALT mode VDD = 5 V10% VDD = 3 V10% VDD = 3 V10% HALT mode VDD = 3 V10% VDD = 5 V10%
VDD = 3 V10%
MIN.
TYP. 2.5 0.35 500 150 30 5 0.5 0.1 0.1
MAX. 8 1.2 1500 450 90 15 20 10 5
Unit mA mA
Supply Current *1 IDD1
A A A A A A A
Ta = 25C
*1: Current for the built-in pull-up resistor is not included. 2: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011. 3: When operated in the low-speed mode with the PCC set to 0000. 4: Including when the subsystem clock is operated. 5: When operated with the subsystem clock by setting the system clock control register (SCC) to 1011 to stop the main system clock operation.
45
PD75004, 75006, 75008
AC CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V)
Parameter CPU Clock Cycle (Minimum Instruction Execution Time = 1 Machine Cycle) TI0 Input Frequency TI0 Input High-, LowLevel Widths Interrupt Input High-, Low-Level Widths Time*1 Symbol tCY Conditions w/main system clock w/subsystem clock fTI tTIH, tTIL tINTH, tINTL VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V INT0 INT1, 2, 4 KR0-7 RESET Low-Level Width tRSL VDD = 4.5 to 6.0 V MIN. 0.95 3.8 114 0 0 0.48 1.8 *2 10 10 10 122 TYP. MAX. 64 64 125 1 275 Unit
s s s
MHz kHz
s s s s s s
*1: The CPU clock () cycle time (minimum instruction execution time) is
70 64 60 6 5 4
Cycle time tCY [s]
tCY vs VDD (with main system clock)
determined by the oscillation frequency of the connected oscillator, system clock control register (SCC), and processor clock control register (PCC). The figure on the right is cycle time tCY vs. supply voltage VDD characteristics at the main system clock. 2: 2tCY or 128/fX depending on the setting of the interrupt mode register (IM0).
Operation guaranteed range
3
2
1
0.5 0 1 2 3 4 5 6 Supply voltage VDD [V]
46
PD75004, 75006, 75008
SERIAL TRANSFER OPERATION Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output):
Parameter SCK Cycle Time SCK High-, Low-Level Widths
SI Set-Up Time (vs. SCK )
Symbol tKCY1 tKL1 tKH1 tSIK1 tKSO1 R = 1 k, C = 100 pF*
Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V
MIN. 1600 3800 tKCY1/2-50 tKCY1/2-150 150 400
TYP.
MAX.
Unit ns ns ns ns ns ns
SI Hold Time (vs. SCK ) tKSI1 SCK SO Output Delay Time VDD = 4.5 to 6.0 V
0 0
250 1000
ns ns
TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input):
Parameter SCK Cycle Time SCK High-, Low-Level Widths
SI Set-Up Time (vs. SCK )
Symbol tKCY2 tKL2 tKH2 tSIK2 tKSI2 tKSO2
Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V
MIN. 800 3200 400 1600 100 400
TYP.
MAX.
Unit ns ns ns ns ns ns
SI Hold Time (vs. SCK ) SCK SO Output Delay Time
R = 1 k, C = 100 pF*
VDD = 4.5 to 6.0 V
0 0
300 1000
ns ns
*: R and C are load resistance and load capacitance of the SO output line.
47
PD75004, 75006, 75008
SBI MODE (SCK: internal clock output (master)):
Parameter SCK Cycle Time SCK High-, Low-Level Widths SB0, 1 Set-Up Time (vs. SCK ) SB0, 1 Hold Time (vs. SCK ) SCK SB0, 1 Output Delay Time SCK SB0, 1 SB0,1 SCK SB0, 1 Low-Level Width SB0, 1 High-Level Width Symbol tKCY3 tKL3 tKH3 tSIK3 tKSI3 tKSO3 tKSB tSBK tSBL tSBH R = 1 k, C = 100 pF* VDD = 4.5 to 6.0 V Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 1600 3800 tKCY3/2-50 tKCY3/2-150 150 tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
SBI MODE (SCK: external clock input (slave)):
Parameter SCK Cycle Time SCK High-, Low-Level Widths SB0, 1 Set-Up Time (vs. SCK ) SB0, 1 Hold Time (vs. SCK ) SCK SB0, 1 Output Delay Time SCK SB0, 1 SB0,1 SCK SB0, 1 Low-Level Width SB0, 1 High-Level Width Symbol tKCY4 tKL4 tKH4 tSIK4 tKSI4 tKSO4 tKSB tSBK tSBL tSBH R = 1 k, C = 100 pF* VDD = 4.5 to 6.0 V Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 800 3200 400 1600 100 tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
*: R and C are load resistance and load capacitance of the SB0 and SB1 output lines.
48
PD75004, 75006, 75008
AC TIMING TEST POINT (excluding X1 and XT1 inputs)
0.8 VDD Test points 0.2 VDD
0.8 VDD 0.2 VDD
CLOCK TIMING
1/fX tXL tXH
X1 input
VDD -0.5V 0.4 V
1/fXT tXTL tXTH
XT1 input
VDD -0.5V 0.4 V
TI0 TIMING
1/fTI tTIL tTIH
TI0
49
PD75004, 75006, 75008
SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE:
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI
Input data
tKSO1
SO
Output data
TWO-LINE SERIAL I/O MODE:
tKCY2 tKL2 tKH2
SCK
tSIK2
tKSI2
SB0,1
tKSO2
50
PD75004, 75006, 75008
SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER:
tKCY3,4 tKL3,4 SCK tSIK3,4 tKH3,4
tKSB
tSBL
tSBH
tSBK
tKSI3,4
SB0,1 tKSO3,4
COMMAND SIGNAL TRANSFER:
tKCY3,4 tKL3,4 SCK tSIK3,4 tKH3,4
tKSB
tSBK
tKSI3,4
SB0,1 tKSO3,4
INTERRUPT INPUT TIMING:
tINTL
tINTH
INT0, 1, 2, 4 KR0-7
RESET INPUT TIMING:
tRSL
RESET
51
PD75004, 75006, 75008
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = -40 to +85C)
Parameter Data Retention Supply Voltage Data Retention Supply Current*1 Release Signal Set Time Oscillation Stabilization Wait Time*2 Symbol VDDDR IDDDR tSREL tWAIT Released by RESET Released by interrupt request VDDDR = 2.0 V 0 217/fX *3 Conditions MIN. 2.0 0.1 TYP. MAX. 6.0 10 Unit V
A s
ms ms
*1: Does not include current flowing through internal pull-up resistor 2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3: Depends on the setting of the basic interval timer mode register (BTM) as follows:
BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1
WAIT time ( ): fXX = 4.19 MHz
2 20/fXX (approx. 250 ms) 2 17/fXX (approx. 31.3 ms) 2 15/fXX (approx. 7.82 ms) 2 13/fXX (approx. 1.95 ms)
DATA RETENTION TIMING
(releasing STOP mode by RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operation mode
VDD VDDDR STOP instruction execution RESET tSREL
tWAIT
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
HALT mode STOP mode Data retention mode Operation mode
VDD VDDDR STOP instruction execution Standby release signal (interrupt request) tSREL
tWAIT
52
PD75004, 75006, 75008
11. CHARACTERISTIC CURVES
IDD vs VDD (Crystal oscillation)
(Ta = 25C)
5000 Main system clock High-speed mode PCC = 0011 Middle-speed mode PCC = 0010 Low-speed mode PCC = 0000 1000 HALT mode
500
Operating current I DD [ A]
Subsystem clock* Operation mode 100
50
HALT mode*
X1 10
X2
XT1
XT2
X'tal 4.19 MHz
X'tal 32.768 kHz 330 k
5
20 pF
18 pF
18 pF
18 pF
1 0 1 2 3 4 5 6 7
Operating voltage V DD [V]
*: Main system clock halts. 53
PD75004, 75006, 75008
IDD vs VDD (Ceramic oscillation)
(Ta = 25C)
5000 Main system clock High-speed mode PCC = 0011 Middle-speed mode PCC = 0010 Low-speed mode PCC = 0000 1000 HALT mode*1
500
Operating current I DD [ A]
Subsystem clock*2 Operation mode 100
50
HALT mode*2
10
X1 X2 Ceramic oscillator
CSA4.19 MGU
XT1 X'tal
XT2 330 k
32.768 kHz
5
30 pF
30 pF
18 pF
18 pF
1 0 1 2 3 4 5 6 7
Operating voltage V DD [V]
*1: When compared to crystal oscillation, increased by approximately 10%. 2: Main system clock halts. 54
PD75004, 75006, 75008
IDD vs VDD (Ceramic oscillation)
(Ta = 25C)
5000
Main system clock High-speed mode PCC = 0011 Middle-speed mode PCC = 0010 Low-speed mode PCC = 0000 HALT mode
1000
500
Operating current I DD [ A]
Subsystem clock* Operation mode 100
50
HALT mode*
10
X1 X2 Ceramic oscillator
CSA2.00MG093
XT1 X'tal
XT2 330 k
32.768 kHz
5
30 pF
30 pF
18 pF
18 pF
1 0 1 2 3 4 5 6 7
Operating voltage V DD [V]
*: Main system clock halts.
55
PD75004, 75006, 75008
3
IDD vs f x X1 X2
(V DD = 5V, Ta = 25C)
2
I DD [mA]
High-speed mode PCC = 0011 Middle-speed mode PCC = 0010
0.5
IDD vs fx
(V DD = 3V, Ta = 25C) X2
Middle-speed High-speed mode mode PCC = 0010 X1 PCC = 0011
0.4
1 Low-speed mode PCC = 0000
I DD [mA]
0.3
Low-speed mode PCC = 0000
0.2
Main system clock HALT mode 0
0.1
Main system clock HALT mode
0 1 2 3 fx [MHz] 4 5
1
2
3 fx [MHz]
4
5
VOL vs I OL (Port 0) 40 (T a = 25C) 40
5 VOL vs I OL (Port 2, 6, 7) (T a = 25C)
30
VDD = 6 V VDD = 5 V V DD = 4 V
30
IOL [mA]
IOL [mA]
20
VDD = 20 6 V
VDD = 5 V V DD = 4 V VDD = 3 V V DD = 2.7 V
VDD = 3 V V DD = 2.7 V 10 10
0
1
2 V OL [V]
3
4
5
0
1
2 V OL [V]
3
4
5
56
PD75004, 75006, 75008
VOL vs I OL (Port 4, 5) 40 (T a = 25C) 40 VOL vs I OL (Port 3) (T a = 25C)
30
VDD = 6 V VDD = 5 V V DD = 4 V
30
VDD = 6 V VDD = 5 V
V DD = 4 V
I OL [mA]
20 VDD = 3 V
I OL [mA]
20 VDD = 3 V
V DD = 2.7 V V DD = 2.7 V 10 10
0
1
2 V OL [V]
3
4
5
0
1
2 V OL [V]
3
4
5
VOH vs IOH
20
(T a = 25C)
15
V DD = 6 V
V DD = 5 V
V DD = 4 V
I OH [mA]
10
V DD = 3 V 5
V DD = 2.7 V
0
1
2
3
4
5
V DD - V OH [V]
57
PD75004, 75006, 75008
12. PACKAGE DRAWINGS
42PIN PLASTIC SHRINK DIP (600 mil)
42 22
1 A
21
K L
I G J H
F C D N
M
B M
R
NOTES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS A B C D F G H I J K L M N R 39.13 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 -0.05 0.17 0~15
INCHES 1.541 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.600 (T.P.) 0.520 0.010 +0.004 -0.003 0.007 0~15 P42C-70-600A-1
58
PD75004, 75006, 75008
5
44 PIN PLASTIC QFP (
10)
A B
33 34
23 22
detail of lead end
C
D
S Q R
44 1
12 11
F G H P
N
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
J I
M
K M L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 13.60.4 10.00.2 10.00.2 13.60.4 1.0 1.0 0.350.10 0.15 0.8 (T.P.) 1.80.2 0.80.2 0.15 +0.10 -0.05 0.10 2.7 0.10.1 55 3.0 MAX. INCHES 0.535 +0.017 -0.016 0.394 +0.008 -0.009 0.394 +0.008 -0.009 0.535 +0.017 -0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.0040.004 55 0.119 MAX. P44GB-80-3B4-3
59
PD75004, 75006, 75008
13. RECOMMENDED SOLDERING CONDITIONS
It is recommended that PD75004, 75006, and 75008 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). The soldering methods and conditions are not listed here, consult NEC. 5
Table 13-1 Soldering Conditions
PD75004GB - xxx - 3B4: 44-pin plastic QFP (s 10 mm) s PD75006GB - xxx - 3B4: 44-pin plastic QFP (s 10 mm) s PD75008GB - xxx - 3B4: 44-pin plastic QFP (s 10 mm) s
Soldering Method Infrared Reflow Soldering Conditions Package peak temperature: 230C, time: 30 seconds max. (210C min.), number of times: 1, number of days: 7 days*, (afterwards, 10 hours of prebaking at 125C is required.) Package peak temperature: 215C, time: 40 seconds max. (200C min.), number of times: 1, number of days: 7 days*, (afterwards, 10 hours of prebaking at 125C is required.) Soldering bath temperature: 260C max., time: 10 seconds max., number of times: 1, number of days: 7 days*, (afterwards, 10 hours of prebaking at 125C is required.) pre-heating temperature: 120C max. (package surface temperature) Pin temperature: 300C max., time: 3 seconds max. (per side) Symbol for Recommended Condition IR30-107-1
VPS
VP15-107-1
Wave Soldering
WS60-00-1
Pin Partial Heating
--
*:
This means the number of days after unpacking the dry pack. Storage conditions are 25C and 65% RH max.
Caution: Do not use two or more soldering methods in combination (except the pin partial heating method).
Table 13-2 Soldering Conditions of Through-Hole Type
PD75004CU - xxx : 42-pin plastic shrink DIP (600 mil) PD75006CU - xxx : 42-pin plastic shrink DIP (600 mil) PD75008CU - xxx : 42-pin plastic shrink DIP (600 mil)
Soldering Method Wave Soldering (Only for lead part) Pin Partial Heating Soldering Conditions Soldering bath temperature: 260C max., Time: 10 seconds max.
Pin temperature: 260C max., Time: 10 seconds max.
Notice A model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235C, number of times: 2, and an extended number of days) is also available. For details, consult NEC.
61
PD75004, 75006, 75008
APPENDIX A. DEVELOPMENT TOOLS
The following development support tools are readily available to support development of systems using
PD75008:
Hardware IE-75000-R *1 IE-75001-R IE-75000-R-EM *2 EP-75008CU/GB-R PG-1500 PA-75P008CU Software IE Control Program PG-1500 Controller RA75X Relocatable Assembler In-circuit emulator for 75X series Emulation board for IE-75000-R and IE-75001-R Emulation prove for PD75004CU/GB, 75006CU/GB, 75008CU/GB PROM programmer PROM programmer adapter solely used for PD75P008CU/GB. It is connected to PG-1500. Host machine TM * PC-9800 series (MS-DOS Ver.3.30 to Ver.5.00A* 3) * IBM PC/ATTM (PC DOS TM Ver.3.1)
*1: Maintenance product 2: Not provided with IE-75001-R. 3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this function.
Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151).
62
PD75004, 75006, 75008
APPENDIX B. RELATED DOCUMENTS
5
63
PD75004, 75006, 75008
[MEMO]
64
PD75004, 75006, 75008
GENERAL NOTES ON CMOS DEVICES
1 STATIC ELECTRICITY (ALL MOS DEVICES)
Exercise care so that MOS devices are not adversely influenced by static electricity while being handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly .
2
PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)
Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its
input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to VDD or GND through a resistor. Refer to "Processing of Unused Pins" in the documents of each devices.
3
STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)
The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the
molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application.
65
PD75004, 75006, 75008
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation.
66

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